1. Technical Field
The present invention generally relates to a semiconductor memory device, and more particularly, to a method for estimating channel characteristics of a nonvolatile memory device.
2. Related Art
In general, a semiconductor memory device is classified into a volatile memory device and a nonvolatile memory device. The volatile memory device loses data stored therein when power supply is cut off, but the nonvolatile memory device maintains data stored therein even though power supply is cut off. The nonvolatile memory device may include various types of memory cells.
The nonvolatile memory device may be divided into a flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change memory device using chalcogenide alloys and the like, depending on the structure of memory cells.
Among the nonvolatile memory devices, the flash memory device is roughly divided into a NOR flash memory device and a NAND flash memory device, depending on the connection state between memory cells and a bit line. The NOR flash memory device has a structure in which two or more memory cell transistors are connected in parallel to one bit line. Therefore, the NOR flash memory device has an excellent random access time characteristic. On the other hand, the NAND flash memory device has a structure in which two or more memory cell transistors are connected in series to one bit line. Such a structure is referred to as a cell string, and one bit line contact is required per one cell string. Therefore, the NAND flash memory device has an excellent characteristic in terms of integration degree.
In the nonvolatile memory devices, a multi-level cell (MLC) structure capable of storing two or more-bit data per one memory cell is widely used. The MLC has a disadvantage in operation speed and error rate, compared to a single-level cell (SLC) structure capable of storing one bit data per one memory cell. However, the use of the MLC structure has increased according to the trend of high capacity of the memory devices.
When n-bit data are to be stored in one memory cell, the memory cell must be programmed to have any one of 2^n threshold voltage distributions. As the size of data to be stored per memory cell increases, that is, n increases, the distance between the respective threshold voltage distributions may be reduced.
However, memory cells arranged in a two-dimensional structure at intersections between word lines and bit lines may be influenced by interference and noise while adjacent memory cells are programmed. Such an influence may change the threshold voltage distributions, and thus the memory cells have a wider threshold voltage distribution than the initial threshold voltage distribution. As a result, read fail rates of the memory cells may increase. Furthermore, due to a disturb phenomenon which may occur during a program operation or read operation, the read fail rates of the memory cells may increase.
As such, the memory cells of the nonvolatile memory device may influenced by various factors, and thus the threshold voltage distributions may be changed. Among the factors, the interference and noise between the memory cells may serve as a main factor to change the threshold voltage distributions. Therefore, when the characteristics of an interference channel and a noise channel are separately estimated, the estimation may be usefully used for designing a signal processing technique.